This invention relates in general to semiconductor devices, and more particularly, to a semiconductor device and a process for generating an etch pattern on a semiconductor device.
During the manufacture of a semiconductor device, it may be necessary to planarize the surface of a semiconductor device as one or more of the manufacturing steps. Chemical Mechanical Polishing is one such process used to planarize surfaces of semiconductor devices. However, it is difficult to guarantee uniformity of the planarization because of varying layouts on the semiconductor device. The nonuniformity in thickness, caused by interactions between the layout and the polishing process, can result in electrical opens, high resistance contacts, electrical shorts, or other leakage paths in the integrated circuits.
Traditionally, tiling has been used in forming semiconductor devices to help solve the varying height problem. Tiles are printed dummy features used to fill in the low areas. There are several ways of choosing where to place the dummy features. A rule based process for tiling, or placing the dummy features, typically includes creating a circuit layout, defining a buffer zone (typically in a range of approximately 0.5-10 microns) around active features within the layout, and combining the circuit layout with the buffer zone to determine excluded areas. All other areas are available for tiling. Rule based tiling places tiles regardless of circuit density. Model based tiling is used to choose locations to place the tiles by taking into account the circuit density and other topographical considerations. However, in some cases, the use of tiles, or dummy features cannot solve all of the layout topographical uniformity problems.
Therefore, a need exists for a way to provide for better topographical uniformity of the surface of a semiconductor device.